Low power and high speed design issues of CMOS  Hamming code generation and error detection circuit at 22 nm and 16 nm channel length of MOS transistor

Author:

Bari SurajitORCID,De Debashis,Sarkar Angsuman

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference20 articles.

1. Chen S-L, Villaverde JF, Lee H-Y, Chung DW-Y, Lin T-L, Tseng C-H, Lo K-A (2017) A power-efficient mixed-signal smart ADC design with adaptive resolution and variable sampling rate for low-power applications. IEEE Sens J 17:3461–3469

2. Floyd L, Jain RP (2006) Digital fundamentals. Pearson Education, New Delhi, India

3. Haykin S (2000) Communication system. Willey, Noida

4. Kang SM, Leblebici Y (2003) CMOS Digital integrated circuits analysis and design. TMH, New Delhi

5. Kennedy G, Davis B (2002) Electronic communication system. TMH, New Delhi

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