Nonplanar switchable arrays-Reference-Cited by-同舟云学术

Nonplanar switchable arrays

Published:1988-06 Issue:2 Volume:7 Page:213-234
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Systems and Signal Process

Author:

Aravena J. L.,Porter W. A.

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/BF01602098.pdf

Reference31 articles.

1. Kung, H. T., Why systolic architectures?,Computer,15, 37–46, 1982.

2. Cappello, P. R., and Steiglitz, K. Unifying VLSI array designs with geometric transformations,Proc. Int. Conf. Parallel Processing, 1983, pp. 448–457.

3. Fortes, J. A. B., Algorithm transformations for parallel processing and VLSI architecture design, Ph.D. dissertation, University of Southern California, Los Angeles, CA, 1983.

4. Hwang, K., and Cheng. Y. H., VLSI computing structure for solving a large-scale linear system of equations,Proc. Int. Conf. Parallel Processing, 1980, pp. 217–227.

5. Kung, H. T., Ruane, L. M. and Yen, D. W. L. A two-level pipelined systolic array for convolutions,VLSI Systems and Computations, pp. 255–264, Computer Science Department, Carnegie-Mellon, 1981.

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