Classification and performance of reconfigurable architectures-Reference-Cited by-同舟云学术

Classification and performance of reconfigurable architectures

Published:1995 Issue: Volume: Page:439-448
ISSN:0302-9743
Container-title:Field-Programmable Logic and Applications
language:
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Author:

Guccione Steven A.,Gonzalez Mario J.

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-60294-1_138.pdf

Reference18 articles.

1. Algotronix, Ltd. CAL1024 Datasheet, 1990.

2. Peter M. Athanas and Harvey F. Silverman. Processor reconfiguration through instruction-set metamorphosis. IEEE Computer, 26(3):11–18, March 1993.

3. Patrice Bertin, Didier Roncin, and Jean Vuillemin. Introduction to programmable active memories. Technical Report 3, DEC Paris Research Laboratory, 1989.

4. Steven Casselman. Virtual computing and the virtual computer. In Duncan A. Buell and Kenneth L. Pocek, editors IEEE Workshop on FPGAs for Custom Computing Machines, pages 43–48, Los Alamitos, CA, April 1993. IEEE Computer Society Press.

5. Pak K. Chan, Martine D. F. Schlag, and Marcelo Martin. BORG: A reconfigurable prototyping board using field-programmable gate arrays. In First International ACM/SIGDA Workshop on Field Programmable Gate Arrays, pages 47–51, 1992.

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