Introduction to a computational theory and implementation of sequential hardware equivalence-Reference-Cited by-同舟云学术

Introduction to a computational theory and implementation of sequential hardware equivalence

Published: Issue: Volume: Page:54-64
ISSN:
Container-title:Lecture Notes in Computer Science
language:
Short-container-title:

Author:

Pixley Carl

Publisher

Springer-Verlag

Link

http://link.springer.com/content/pdf/10.1007/BFb0023719.pdf

Reference11 articles.

1. C. Pixley, A Computational Theory and Implementation of Sequential Hardware Equivalence, DIMACS Technical Report 90–31, volume 2, Workshop on Computer-Aided Verification June 18–21, Robert Kurshan and E.M. Clarke, eds.

2. O. Coudert, C. Berthet, Jean Christolphe Madre, Verification of Sequential Machines Using Boolean Functional Vectors, Proceedings of the IMEC-IFIP International Workshop on Applied Formal Methods For Correct VLSI Design, November 13–16, 1989.

3. R.E. Bryant, Graph-Based Algorithms for Boolean Function Manipulation, IEEE Transactions on Computers, Vol. C35 No. 8, August 1986.

4. R.E. Bryant, Can a Simulator Verify a Circuit?, Formal Aspects of VLSI Design, eds. G.J.Milne et al., North-Holland, 1966.

5. J.E.Hopcroft, J.D.Ullman, Formal Languages and Their Relation to Automata, Addison-Wesley, 1969.

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. SE3: Sequential Equivalence Checking for Non-Cycle-Accurate Design Transformations ^†;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

2. On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking;Lecture Notes in Computer Science;2003

3. Reachability analysis of large circuits using disjunctive partitioning and partial iterative squaring;Journal of Systems Architecture;2001-02

4. FILL and FUNI;ACM Transactions on Design Automation of Electronic Systems;2000-07

5. The verification problem for safe replaceability;Computer Aided Verification;1994