The method of reducing the CMOS inverter switching energy-Reference-Cited by-同舟云学术

The method of reducing the CMOS inverter switching energy

Published:2023-08-11 Issue:12 Volume:13 Page:7501-7511
ISSN:2190-5509
Container-title:Applied Nanoscience
language:en
Short-container-title:Appl Nanosci

Author:

Druzhinin Anatoly,Kogut Igor,Holota Victor,Nichkalo Stepan,Khoverko Yuriy,Benko Taras

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Cell Biology,Physical and Theoretical Chemistry,Materials Science (miscellaneous),Atomic and Molecular Physics, and Optics,Biotechnology

Link

https://link.springer.com/content/pdf/10.1007/s13204-023-02929-9.pdf

Reference16 articles.

1. Abdalla Y (2012) Reduction of short circuit current in static CMOS inverters using novel smart delay generator circuits. Elektrotech Inftech 129:83–87. https://doi.org/10.1007/s00502-012-0079-z

2. Bisduonis L (2010) Short-circuit energy dissipation model for sub-100 nm CMOS buffers. 17th IEEE Int Conf on Electronics, Circuits and Systems (ICECS), pp. 615–618

3. Chabini N, Chabini I, Aboulhamid EM, Savaria Y (2003) Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Trans Comput Aided Des Integr Circuits Syst. https://doi.org/10.1109/TCAD.2002.807894

4. Donno M, Ivaldi A, Benini L, Macii E (2003) Clock-tree power optimization based on RTL clock-gating. Proceedings of the 40th Annual Design Automation Conference. Anaheim CA USA: Association for Computing Machinery (ACM), pp. 622–627. https://doi.org/10.1145/775832.775989

5. Guo J, Ge H, Ye J, Emadi A. (2015) Improved method for MOSFET voltage rise-time and fall-time estimation in inverter switching loss calculation. IEEE Transportation Electrification Conference and Expo (ITEC), pp. 1–6. https://doi.org/10.1109/ITEC.2015.7165790