Embedding binary tree in VLSI/WSI processor array
Author:
Publisher
Springer Science and Business Media LLC
Subject
Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software
Link
http://link.springer.com/content/pdf/10.1007/BF02943138.pdf
Reference7 articles.
1. Belkhale K P, Banerjee P. Reconfiguration strategies for VLSI arrays and trees using a modified diogense approach.IEEE Trans. on Computers, 1992, C-41(1): 83–96.
2. Singh A, Youn H Y. Modular fault-tolerant binary tree architecture with short links.IEEE Trans. on Computers, 1991, C-40(7): 882–890.
3. Chen Y Y, Upadhyaya S. Reliability, re-configuration, and spare allocation issues in binary architecture based on multiple-level redundancy.IEEE Trans. on Computers, 1993, C-42(6): 713–723.
4. Lowrie M B, Fuchs W K. Reconfigurable tree architectures using subtree oriented fault tolerance.IEEE Trans. on Computers, 1987, C-36(10): 1172–1182.
5. Howells M C, Agarwal V K. A re-configuration scheme for yield enhancement of large area binary tree architectures.IEEE Trans. on Computers, 1988, C-37(4): 463–468.
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