Design verification of a microprocessor using branching time regular temporal logic-Reference-Cited by-同舟云学术

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Design verification of a microprocessor using branching time regular temporal logic

Published:1993 Issue: Volume: Page:206-219
ISSN:0302-9743
Container-title:Computer Aided Verification
language:
Short-container-title:

Author:

Hamaguchi Kiyoharu,Hiraishi Hiromi,Yajima Shuzo

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-56496-9_17.pdf

Reference13 articles.

1. R. E. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, C-35(8):677–691, August 1986.

2. Shinichi Minato, Nagisa Ishiura, and Shuzo Yajima. Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean Function Manipulation. In Proceedings of 27th Design Automation Conference, pages 52–57, 1990.

3. K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient Implementation of a BDD Package. In Proceedings of 27th Design Automation Conference, pages 40–45, 1990.

4. J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential Circuit Verification Using Symbolic Model Checking. In Proceedings of 27th Design Automation Conference, pages 46–51, 1990.

5. J. R. Burch, E. M. Clarke, and D. E. Long. Representing Circuits More Efficiently in Symbolic Model Checking. In Proceedings of 28th Design Automation Conference, pages 403–407, June 1991.

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