Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits

Author:

McMillan K. L.

Publisher

Springer Berlin Heidelberg

Reference13 articles.

1. J. R. Burch, E. M. Clarke, and D. E. Long. Symbolic model checking with partitioned transition relations. To appear in the Proceedings of VLSI'91.

2. J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, and J. Hwang. Symbolic model checking: 1020 states and beyond. In Proceedings of the Fifth Annual Symposium on Logic in Computer Science, June 1990.

3. D. Dill. Trace theory for automatic hierarchical verification of speed-independent circuits. Technical Report 88-119, Carnegie Mellon University, Computer Science Dept, 1988.

4. P. Godefroid. Using partial orders to improve automatic verification methods. In Workshop on Computer Aided Verification, 1990.

5. P. Godefroid and P. Wolper. A partial approach to model checking. In LICS, 1991.

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