Automated design of error-resilient and hardware-efficient deep neural networks

Author:

Schorn Christoph,Elsken Thomas,Vogel Sebastian,Runge Armin,Guntoro Andre,Ascheid Gerd

Publisher

Springer Science and Business Media LLC

Subject

Artificial Intelligence,Software

Reference112 articles.

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2. Aitken R, Cannon EH, Pant M, Tahoori MB (2015) Resiliency challenges in sub-10nm technologies. In: IEEE 33rd VLSI Test Symposium (VTS), pp 1–4. https://doi.org/10.1109/VTS.2015.7116281

3. Azizimazreah A, Gu Y, Gu X, Chen L (2018) Tolerating soft errors in deep learning accelerators with reliable on-chip memory designs. In: IEEE international conference on networking, architecture and storage (NAS), pp 1–10. https://doi.org/10.1109/NAS.2018.8515692

4. Bach S, Binder A, Montavon G, Klauschen F, Müller KR, Samek W (2015) On pixel-wise explanations for non-linear classifier decisions by layer-wise relevance propagation. PLoS ONE. https://doi.org/10.1371/journal.pone.0130140

5. Baker B, Gupta O, Naik N, Raskar R (2017) Designing neural network architectures using reinforcement learning. In: International conference on learning representations (ICLR)

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