Author:
Bandyopadhyay Soumyadip,Sarkar Dipankar,Mandal Chittaranjan
Publisher
Springer Science and Business Media LLC
Subject
Computer Networks and Communications,Information Systems,Software
Reference56 articles.
1. Arendt, F., Kluhe, B.: Modelling and verification of real-time software using interpreted petri nets. Ann. Rev. Autom. Programm. 15, 35–40 (1990)
2. Armstrong, D.B.: A programmed algorithm for assigning internal codes to sequential machines. IRE. Trans. Elect. Comput., EC-11, Aug (1962)
3. Baier, C., Katoen, J.-P.: Principles of Model Checking. MIT Press, Cambridge (2008)
4. Bandyopadhyay, S., Banerjee, K., Sarkar, D., Mandal, C.: Translation validation for pres+ models of parallel behaviours via an fsmd equivalence checker. In: Progress in VLSI Design and Test (VDAT), vol. 7373, pp. 69–78. Springer, (2012)
5. Bandyopadhyay, S., Banerjee, K.: Presgen: A fully automatic equivalence checker for validating optimizing and parallelizing transformations. In: Proceedings of the 2017 Workshop on Software Engineering Methods for Parallel and High Performance Applications, SEM4HPC ’17, pp. 13–20 (2017)
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