Author:
Pham Anh-Tuan,Jungemann Christoph,Meinerzhagen Bernd
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Modeling and Simulation,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference36 articles.
1. Engl, W.L., et al.: Device modeling. Proc. IEEE 71, 10 (1983)
2. Thompson, S., et al.: A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 um2 SRAM cell. In: IEDM Tech. Dig. p. 61 (2002)
3. Mistry, K., et al.: A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. In: IEDM Tech. Dig., pp. 247–250 (2007)
4. Krishnamohan, T., et al.: Comparison of (001), (110) and (111) Uniaxial- and biaxial-strained-Ge and strained-Si PMOS DGFETs for all channel orientations: mobility enhancement, drive current, delay and off-state leakage. In: IEDM Tech. Dig. (2008)
5. Grasser, T., et al.: A non-parabolic macroscopic transport models for device simulation based on bulk Monte Carlo data. J. Appl. Phys. 97, 093710 (2005)
Cited by
10 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献