1. D.G. Thakurta, D.W. Schwendeman, R.J. Gutmann, and S. Shankar, “Three-dimensional wafer-scale copper chemical-mechanical planarization model,” Thin Solid Films, 414(1), 78 (2002).
2. V.K. Singh and J. Garcia-Colevatti, “Relevance of TCAD to process-aware design,” Proceedings of the SPIE, 4692, 405 (2002).
3. M. Bohr, S.U. Ahmed, L. Brigham, R. Chau, R. Gasser, R. Green, W. Hargrove, E. Lee, R. Natter, S. Thompson, K. Weldon, and S. Yang, “A high performance 0.3 μm logic technology for 3.3 V and 2.5 V operation,” in 1994 IEEE International Electron Devices Meeting Proceedings, p.273.
4. M.D. Giles, M. Armstrong, C. Auth, S.M. Cea, T. Ghani, T. Hoffmann, R. Kotlyar, P. Matagne, K. Mistry, R. Nagisetty, B. Obradovic, R. Shaheed, L. Shifren, M. Stettler, S. Tyagi, X. Wang, C. Weber, and K. Zawadzki, “Understanding stress enhanced performance in Intel 90 nm CMOS technology,” 2004 Symposium on VLSI Technology, (2004) p. 118.
5. B. Obradovic, P. Matagne, L. Shifren, X. Wang, M. Stettler, J. He, and M.D. Giles, “A physically-based analytic model for stress-induced hole mobility,” Tenth International Workshop on Computational Electronics (2004).