Modeling of modern MOSFETs with strain
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Published:2009-10
Issue:3-4
Volume:8
Page:192-208
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ISSN:1569-8025
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Container-title:Journal of Computational Electronics
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language:en
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Short-container-title:J Comput Electron
Author:
Sverdlov V.,Baumgartner O.,Windbacher T.,Selberherr S.
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Modeling and Simulation,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference71 articles.
1. Doris, B., Ieong, M., Kanarsky, T., Zhang, Y., Roy, R.A., Documaci, O., Ren, Z., Jamin, F.-F., Shi, L., Natzle, W., Huang, H.-J., Mezzapelle, J., Mocuta, A., Womack, S., Gribelyuk, M., Jones, E.C., Miller, R.J., Wong, H.-S.P., Haensch, W.: Extreme scaling with ultra-thin Si channel MOSFETs. In: IEDM Tech. Dig., pp. 267–270 (2002) 2. Natarajan, S., Armstrong, M., Bost, M., Brain, R., Brazier, M., Chang, C., Chikarmane, V., Childs, M., Deshpande, H., Dev, K., Ding, G., Ghani, T., Golonzka, O., Han, W., He, J., Heussner, R., James, R., Jin, I., Kenyon, C., Klopcic, S., Lee, S., Liu, M., Lodha, S., McFadden, B., Murthy, A., Neiberg, L., Neirynck, J., Packan, P., Pae, S., Parker, C., Pelto, C., Pipes, L., Sebastian, J., Seiple, J., Sell, B., Sivakumar, S., Song, B., Tone, K., Troeger, T., Weber, C., Yang, M., Yeoh, A., Zhang, K.: A 32 nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171 μm2 SRAM cell size in a 291 Mb array. In: IEDM Tech. Dig., pp. 941–943 (2008) 3. Mistry, K., Allen, C., Auth, C., Beattie, B., Bergstrom, D., Bost, M., Brazier, M., Buehler, M., Cappellani, A., Chau, R., Choi, C., Ding, G., Fischer, K., Ghani, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., He, J., Hicks, J., Huessner, R., Ingerly, D., Jain, P., James, R., Jong, L., Joshi, S., Kenyon, C., Kuhn, K., Lee, K., Liu, H., Maiz, J., McIntyre, B., Moon, P., Neirynck, J., Pae, S., Parker, C., Parsons, D., Prasad, C., Pipes, L., Prince, M., Rarade, P., Reynolds, T., Sandford, J., Shifren, L., Sebastian, J., Seiple, J., Simon, D., Sivakumar, S., Smith, P., Thomas, C., Troeger, T., Vandervoorn, P., Williams, S., Zawadzki, K.: A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. In: IEDM Tech. Dig., pp. 247–250 (2007) 4. Hudait, M.K., Dewey, G., Datta, S., Fastenau, J.M., Kavalieros, J., Liu, W.K., Lubyshev, D., Pillarisetty, R., Rachmady, W., Radosavljevic, M., Rakshit, T., Chau, R.: Heterogeneous integration of enhancement mode in 0.7 Ga 0.3 As quantum well transistor on silicon substrate using thin (≤2 μm) composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications. In: IEDM Tech. Dig., pp. 625–628 (2007) 5. Chau, R.: Challenges and opportunities of emerging nanotechnology for future VLSI nanoelectronics. In: Rec. International Semiconductor Device Research Symposium (ISDRS), p. 3 (2007)
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