Modeling of modern MOSFETs with strain

Author:

Sverdlov V.,Baumgartner O.,Windbacher T.,Selberherr S.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Modeling and Simulation,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference71 articles.

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3. Mistry, K., Allen, C., Auth, C., Beattie, B., Bergstrom, D., Bost, M., Brazier, M., Buehler, M., Cappellani, A., Chau, R., Choi, C., Ding, G., Fischer, K., Ghani, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., He, J., Hicks, J., Huessner, R., Ingerly, D., Jain, P., James, R., Jong, L., Joshi, S., Kenyon, C., Kuhn, K., Lee, K., Liu, H., Maiz, J., McIntyre, B., Moon, P., Neirynck, J., Pae, S., Parker, C., Parsons, D., Prasad, C., Pipes, L., Prince, M., Rarade, P., Reynolds, T., Sandford, J., Shifren, L., Sebastian, J., Seiple, J., Simon, D., Sivakumar, S., Smith, P., Thomas, C., Troeger, T., Vandervoorn, P., Williams, S., Zawadzki, K.: A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. In: IEDM Tech. Dig., pp. 247–250 (2007)

4. Hudait, M.K., Dewey, G., Datta, S., Fastenau, J.M., Kavalieros, J., Liu, W.K., Lubyshev, D., Pillarisetty, R., Rachmady, W., Radosavljevic, M., Rakshit, T., Chau, R.: Heterogeneous integration of enhancement mode in 0.7 Ga 0.3 As quantum well transistor on silicon substrate using thin (≤2 μm) composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications. In: IEDM Tech. Dig., pp. 625–628 (2007)

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