Comparative of analog performance of transcapacitances in asymmetric self-cascode and graded-channel SOI nMOSFETs
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Modeling and Simulation,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s10825-022-01998-3.pdf
Reference8 articles.
1. Colinge, J.P.: Silicon-On-insulator technology: materials to VLSI, In: 3rd ed. Massachusetts, Kluwer Academic (2004)
2. De Souza,M., Flandre, D., Pavanello, M.A.: Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors, In 2013 Symposium on Microelectronics Technology and Devices (SBMicro), Sep. 2013, pp. 1–4. https://doi.org/10.1109/SBMicro.2013.6676154
3. Sanz, M.T., Celma, S., Calvo, B., Flandre, D.: Self-cascode SOI versus graded-channel SOI MOS transistors. Circuits Devices Syst. IEEE Proc. 153, 461–465 (2006). https://doi.org/10.1049/ip-cds:20060058
4. Galup-Montoro, C., Schneider, M.C., Loss, I.J.B.: Series-parallel association of FET’s for high gain and high frequency applications. IEEE J. Solid-State Circuits 29(9), 1094–1101 (1994). https://doi.org/10.1109/4.309905
5. De Souza,M., Flandre, D., Pavanello, M.A.: Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors, In: SOI Conference (SOI), IEEE International, Oct. 2011, pp. 1–2. https://doi.org/10.1109/SOI.2011.6081716
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