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2. Berkeley: Berkeley logic interchange format (blif). http://www.cs.uic.edu/~jlillis/courses/cs594/spring05/blif.pdf—resume of blif, not an academic paper (2005)
3. Biere, A.: The AIGER and-inverter graph (AIG) format (2007). http://fmv.jku.at/aiger/
4. Brglez, F., Fujiwara, H.: A neutral netlist of 10 combinational Benchmark circuits and a target translator in Fortran. In: Proceedings of IEEE International Symposium Circuits and Systems (ISCAS 85), pp. 677–692. IEEE Press, Piscataway (1985)
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