Author:
Barra Samir,Kouda Souhil,Dendouga Abdelghani,Bouguechal N. E.
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Computer Science Applications,Modelling and Simulation,Control and Systems Engineering
Reference20 articles.
1. S. W. Sin, U. Seng-Pan, R. P. Martins. 1. 2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18¼m CMOS with minimised supply headroom. IET Circuits Devices & Systems, vol. 4, no. 1, pp. 1–3, 2010.
2. J. F. Lin, S. J. Chang, C. C. Liu, C. H. Huang. A 10bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique. IEEE Transactions on Circuits and Systems, vol. 57, no. 3, pp. 163–167, 2010.
3. E. Bilhan, P. C. Estrada-Gutierrez, A. Y. Valero-Lopez, F. Maloberti. Behavioral model of pipeline ADC by using SIMULINK (R). In Proceedings of Southwest Symposium on Mixed-signal Design, IEEE, Austin, TX, USA, pp.147–151, 2001.
4. M. Ramalatha, A. P. Karthick, S. Karthick, K. Muralikr-ishnan. A high speed 12-bit pipelined ADC using switched capacitor and fat tree encoder. In Proceedings of International Conference on Advances in Computational Tools for Engineering Applications, IEEE, Zouk Mosbeh, Lebanon, pp. 391–395, 2009.
5. J. Ruiz-Amaya, M. Delgado-Restituto, Á. Rodríguez-Vázquez. Behavioral modeling of pipeline ADC building blocks. International Journal of Circuit Theory and Applications, vol. 40, no. 6, pp. 571–594, 2012.
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献