Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs

Author:

Buyukkurt Betul,Guo Zhi,Najjar Walid A.

Publisher

Springer Berlin Heidelberg

Reference20 articles.

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2. Park, J., Diniz, P.C., Shayee, K.R.S.: Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. IEEE Transactions on Computers 53(11), 1420–1435 (2004)

3. SUIF Compiler System (2004), http://suif.stanford.edu

4. Machine-SUIF (2004), http://www.eecs.harvard.edu/hube/research/machsuif.html

5. Guo, Z., Najjar, W., Vahid, F., Vissers, K.: A Quantitative Analysis of the Speedup Factors of FPGAs over Processors. In: Symp. on Field-Programmable gate Arrays (FPGA), Monterrey, CA (February 2004)

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