Exact Settling Performance Design for CMOS Three-Stage Nested-Miller-Compensated Amplifiers
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-022-02172-7.pdf
Reference33 articles.
1. S.R. Afrancheh, et al, Design procedure for settling time minimization in three-stage RNMC amplifiers, in IEEE EUROCON—International Conference on Computer as a Tool (Lisbon, Portugal, 2011). https://doi.org/10.1109/EUROCON.2011.6174587
2. H. Aminzadeh, Three-stage nested-Miller-compensated operational amplifiers: analysis, design, and optimization based on settling time. Int. J. Circuit Theory Appl. 39, 573–587 (2011). https://doi.org/10.1002/cta.663
3. E. Cabrera-Bernal et al., 0.7-V three-stage class-AB CMOS operational transconductance amplifier. IEEE Trans. Circuits Syst. I 63(11), 1807–1815 (2016). https://doi.org/10.1109/TCSI.2016.2597440
4. S.O. Cannizzaro et al., Design procedures for three-stage CMOS OTAs with nested-Miller compensation. IEEE Trans. Circuits Syst. I 54(5), 933–940 (2007). https://doi.org/10.1109/TCSI.2007.895520
5. A.M.L. Canelas, J.M.C. Guilherme, N.C.G. Horta, Yield-aware analog IC design and optimization in nanometer-scale technologies. Springer (2020). https://doi.org/10.1007/978-3-030-41536-5
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