PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-022-02159-4.pdf
Reference24 articles.
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2. A. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, P. H. Madden, Fractional cut: improved Recursive Bisection Placement. In Proceedings of the 2003 IEEE/ACM international conference on Computer-aided Design, IEEE Computer Society, 307–310 (2003). https://doi.org/10.1109/ICCAD.2003.1257685
3. A. Alhyari, A. Shamli, Z. Abuwaimer, S. Areibi, G. Grewal, A Deep Learning Framework to Predict Routability for FPGA Circuit Placement. 29th International Conference on Field Programmable Logic and Applications (FPL), 334–341 (2019). https://doi.org/10.1109/FPL.2019.00060
4. U. Brenner, M. Struzyna, J. Vygen, BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms. In IEEE Trans. Computer-Aided Design Integrated Circuits Syst 27(9), 1607–1620 (2008). https://doi.org/10.1109/TCAD.2008.927674
5. U. Brenner, A. Rohe, An effective congestion-driven placement framework. In IEEE Trans Computer-Aided Design Integr Circuits Syst 22(4), 387–394 (2003). https://doi.org/10.1109/TCAD.2003.809662
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