High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder-Reference-Cited by-同舟云学术

High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder

Published:2017-09-25 Issue:6 Volume:37 Page:2492-2510
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Syst Signal Process

Author:

Abdel-Hafeez Saleh,Shatnawi Ali

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

http://link.springer.com/article/10.1007/s00034-017-0673-8/fulltext.html

Reference21 articles.

1. S. Abdel-Hafeez, A new high-speed SAR ADC architecture, in 2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD) (IEEE, 2010), pp. 1–5

2. H.Y. Chang, C.Y. Yang, A high-speed low-power calibrated flash ADC, in 2014 IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE, 2014), pp. 2369–2372

3. K. Duwada, V. Saxena, R.J. Baker, High speed digital input buffer circuits, in 2006 IEEE Workshop on Microelectronics and Electron Devices, 2006. WMED’06 (IEEE, 2006), pp. 2-pp

4. J.K. Fiorenza, T. Sepke, P. Holloway, C.G. Sodini, H.S. Lee, Comparator-based switched-capacitor circuits for scaled CMOS technologies. IEEE J. Solid-State Circuits 41(12), 2658–2668 (2006)

5. B. Goll, H. Zimmermann, Low-power 600 MHz comparator for 0.5 V supply voltage in 0.12 lm CMOS. Electron. Lett. 43(7), 388–390 (2007)

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