An 11-bit Nyquist SAR-VCO Hybrid ADC with a Reused Ring-VCO for Power Reduction
Author:
Funder
National Natural Science Foundation of China
Key Scientific Research Program of Shaanxi Provincial Department of Education
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-023-02531-y.pdf
Reference37 articles.
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2. Z. Ding, X. Zhou, Q. Li, A 0.5–1.1-V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator. IEEE J. Solid-State Circuits 54(4), 968–977 (2019). https://doi.org/10.1109/JSSC.2018.2885554
3. A. Gupta, K. Nagaraj, T. Viswanathan, A two-stage ADC architecture with VCO-based second stage. IEEE Trans. Circuits Syst. II Express Briefs 58(11), 734–738 (2011). https://doi.org/10.1109/TCSII.2011.2168015
4. S. Hsieh, C. Kao, C. Hsieh, A 0.5-V 12-bit SAR ADC using adaptive time-domain comparator with noise optimization. IEEE J. Solid-State Circuits 53(10), 2763–2771 (2018). https://doi.org/10.1109/JSSC.2018.2862880
5. W. Huang, S. Liu, Sub-1 V capacitor-free low-dropout regulator. Electron. Lett. 42(24), 1395–1396 (2006). https://doi.org/10.1049/el:20062871
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