A Novel Decimal Logarithmic Converter Based on First-Order Polynomial Approximation
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s00034-011-9365-y.pdf
Reference14 articles.
1. K.H. Abed, R.E. Siferd, CMOS VLSI implementation of a low-power logarithmic converter. IEEE Trans. Comput. 52(11), 1421–1433 (2003)
2. D. Chen, Y. Choi, L. Chen, D. Teng, K. Wahid, S. Ko, A novel decimal-to-decimal logarithmic converter, in Proceedings of 2008 IEEE International Symposium on Circuit and System, Seattle, USA (2008), pp. 688–691
3. M. Combet, H. Van Zonneveld, L. Verbeek, Computation of the base two logarithm of binary numbers. IEEE Trans. Electron. Comput. 14, 863–867 (1965)
4. M.F. Cowlishaw, Decimal floating-point: algorithm for computers, in Proceedings of 16th IEEE Symposium on Computer Arithmetic, Washington, USA (2003), pp. 104–111
5. J.-P. Deschamps, G.J.A. Bioul, G.D. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems (Wiley, Hoboken, 2006)
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