A Low Error, Hardware Efficient Logarithmic Multiplier
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-021-01793-8.pdf
Reference34 articles.
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2. K.H. Abed, R.E. Siferd, Vlsi implementation of a low-power antilogarithmic converter. IEEE Trans. Comput. 52(9), 1221–1228 (2003). https://doi.org/10.1109/TC.2003.1228517
3. M.S. Ansari, B.F. Cockburn, J.A. Han, Hardware-efficient logarithmic multiplier with improved accuracy. In: 2019 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 928–931 (2019). https://doi.org/10.23919/DATE.2019.8714868
4. M.S. Ansari, B.F. Cockburn, J. Han, An improved logarithmic multiplier for energy-efficient neural computing. IEEE Trans. Comput. 70(4), 614–625 (2021). https://doi.org/10.1109/TC.2020.2992113
5. M.G. Arnold, C. Walter, Unrestricted faithful rounding is good enough for some lns applications. In: Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, pp. 237–246 (2001). https://doi.org/10.1109/ARITH.2001.930125
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