Hardware Architectures for Computing Eigendecomposition-Based Discrete Fractional Fourier Transforms with Reduced Arithmetic Complexity-Reference-Cited by-同舟云学术

Hardware Architectures for Computing Eigendecomposition-Based Discrete Fractional Fourier Transforms with Reduced Arithmetic Complexity

Published:2023-09-01 Issue:1 Volume:43 Page:593-614
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Syst Signal Process

Author:

Bispo Breno C.^ORCID,de Oliveira Neto José R.^ORCID,Lima Juliano B.^ORCID

Funder

Conselho Nacional de Desenvolvimento Científico e Tecnológico

Fundação de Amparo à Ciência e Tecnologia do Estado de Pernambuco

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

https://link.springer.com/content/pdf/10.1007/s00034-023-02493-1.pdf

Reference31 articles.

1. A. Acharya, S. Mukherjee, Designing a re-configurable fractional Fourier transform architecture using systolic array. Int. J. Comput. Sci. Issues 7, 159 (2010)

2. R.E. Blahut, Fast Algorithms for Signal Processing (Cambridge University Press, Cambridge, 2010). https://doi.org/10.1017/cbo9780511760921

3. C. Candan, M. Kutay, H. Ozaktas, The discrete fractional Fourier transform. IEEE Trans. Signal Process. 48(5), 1329–1337 (2000). https://doi.org/10.1109/78.839980

4. C. Candan, On higher order approximations for Hermite–Gaussian functions and discrete fractional Fourier transforms. IEEE Signal Process. Lett. 14(10), 699–702 (2007). https://doi.org/10.1109/LSP.2007.898354

5. A. Cariow, J. Papliński, D. Majorkowska-Mech, Some structures of parallel VLSI-oriented processing units for implementation of small size discrete fractional Fourier transforms. Electronics 8(5), 509 (2019). https://doi.org/10.3390/electronics8050509