Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Reference14 articles.
1. H. Adachi et al, Design of CMOS resonating push–push frequency doubler, in IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), Kyoto (2014), p. 1–2
2. S. D’Amico, A. Donno, M. Conta, A. Baschirotto, A 6.1 mW 7.5–10.6 GHz PLL-based frequency synthesizer for IEEE 802.15.4a UWB transceivers. Analog Integr. Circuits Signal Process. 88(3), 383–389 (2016)
3. G.S. Jeong, W. Kim, J. Park, T. Kim, H. Park, D.K. Jeong, A
$$0.015-\text{ mm }^{2}$$
0.015
-
mm
2
Inductorless 32-GHz clock generator with wide frequency-tuning range in 28-nm CMOS technology. IEEE Trans. Circuits Syst. II: Express Briefs 64(6), 655–659 (2017)
4. H. Jia, L. Kuang, Z. Wang, B. Chi, A W-band injection-locked frequency doubler based on top-injected coupled resonator. IEEE Trans. Microw. Theory Techn. 64(1), 210–218 (2016)
5. I. Ju, C.D. Cheon, J.D. Cressler, A compact highly efficient high-power Ka-band SiGe HBT cascode frequency doubler with four-way input transformer Balun. IEEE Trans. Microw. Theory Techn. 66(6), 2879–2887 (2018)