An Efficient FPGA Architecture for Reconfigurable FFT Processor Incorporating an Integration of an Improved CORDIC and Radix-2r Algorithm
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-020-01436-4.pdf
Reference31 articles.
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2. H. Abdoli, H. Nikmehr, A flexible CO-OFDM using reconfigurable multi-precision FFT. IEEE Commun. Lett. 21, 1997–2000 (2017)
3. S. Aggarwal, P. Meher, K. Khare, Concept, design, and implementation of reconfigurable CORDIC. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24, 1588–1592 (2016)
4. R Andraka A survey of CORDIC algorithms for FPGA based computers. in Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays 1998 pp. 191–200
5. M. Bahtat, S. Belkouch, P. Elleaume, P. Le Gall, Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage. EURASIP J. Adv. Signal Process. 2016(1), 38 (2016)
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