Hardware Implementation of a High-Speed Adaptive Filter Using a Combination of Systolic and Convex Architectures
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-023-02539-4.pdf
Reference27 articles.
1. M. Bahoura, H. Ezzaidi, FPGA-implementation of parallel and sequential architectures for adaptive noise cancelation. Circuits Syst Signal Process 30, 1521–1548 (2011). https://doi.org/10.1007/s00034-011-9310-0
2. M. Chandra, P. Goel, A. Anand, A. Kar, Design and analysis of improved high-speed adaptive filter architectures for ECG signal denoising. Biomed. Signal Process. Control (2021). https://doi.org/10.1016/j.bspc.2020.102221
3. F. Ding, Y. Wang, J. Ding, Recursive least squares parameter identification algorithms for systems with colored noise using the filtering technique and the auxilary model. Digit. Signal Process. 37, 100–108 (2015). https://doi.org/10.1016/j.dsp.2014.10.005
4. V. Filipovic, N. Nedic, V. Stojanovic, Robust identification of pneumatic servo actuators in the real situations. Forsch. Ing. 75, 183–196 (2011). https://doi.org/10.1007/s10010-011-0144-5
5. P. Goel, M. Chandra, FPGA implementation of adaptive filtering algorithms for noise cancellation—a technical survey. in Proceedings of the Third International Conference on Microelectronics, Computing and Communication Systems. Lecture Notes in Electrical Engineering, ed by V. Nath, J. Mandal. vol 556. (Springer, Singapore, 2019) doi:https://doi.org/10.1007/978-981-13-7091-5_42
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