Balance testing and balance-testable design of logic circuits-Reference-Cited by-同舟云学术

Balance testing and balance-testable design of logic circuits

Published:1996-02 Issue:1 Volume:8 Page:71-86
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Chakrabarty Krishnendu,Hayes John P.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/BF00136077.pdf

Reference27 articles.

1. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990.

2. J.P. Hayes, ?Check Sum Methods for Test Data Compression,? Journal of Design Automation and Fault-Tolerant Computing, vol. 1, pp. 3?7, January 1976.

3. A. Tzidon, I. Berger, and M. Yoeli, ?A Practical Approach to Fault Detection in Combinational Circuits,? IEEE Transactions on Computers, vol. C-27, pp. 968?971, October 1978.

4. J. Savir, ?Syndrome-Testable Design of Combinational Circuits,? IEEE Transactions on Computers, vol. C-29, pp. 442?451, June 1980.

5. R.A. Frohwerk, ?Signature Analysis: A New Digital Field Service Method,? Hewlett-Packard Journal, vol. 28, pp. 2?8, September 1977.

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