Timing slack optimization approach using FPGA hybrid routing strategy of rip-up-retry and pathfinder

Author:

Yu Wei,Yang Haigang,Liu Yang,Huang Juan

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference16 articles.

1. B. Yao, A. Sinha, and I. Pomeranz. Path selection based on static timing analysis considering input necessary assignments. The 31st VLSI Test Symposium Proceedings, Berkeley, CA, USA, April 30–May 2, 2013, 1–6.

2. S. Onaissi, F. Taraporevala, Liu Jinfeng, and F. Najm. A fast approach for static timing analysis covering all PVT corners. The 48th IEEE Design Automation Conference, San Diego, CA, USA, June 2–6, 2011, 777–782.

3. S. Ahmed, D. Das, D. Petranovic, and Y. Ismail. A novel moment based framework for accurate and efficient static timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(2011)8, 1258–1262.

4. M. Orshansky and K. Keutzer. A general probabilistic framework for worst case timing analysis. The 39th IEEE Design Automation Conference, New Orleans, LA, USA, June 10–14, 2002, 556–561.

5. E. Yahya, L. Fesquet, Y. Ismail, and M. Renaudin. Statistical static timing analysis of conditional asynchronous circuits using model-based simulation. The 19th International Symposium on Asynchronous Circuits and Systems, Santa Monica, CA, USA, May 19–22, 2013, 67–74.

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