Ground bouncing noise reduction technique considering wake-up delay in MTCMOS circuits
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s11767-012-0706-1.pdf
Reference12 articles.
1. Siva G. Narendra and A. Chandrakasan. Leakage in Nanometer CMOS Technologies. New York, Springer-Verlag, 2006, 6–19.
2. S. Mutoh, T. Douseki, and Y. Matsuya, et al. 1-V power supply high-speed digital circuit technology. IEEE Journal of Solid-State Circuits, 30(1995)8, 847–854.
3. H. Kawaguchi, K. Nose, and T. Sakura. A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere standby current. IEEE Journal of Solid-State Circuits, 35(2000)10, 1498–1501.
4. S. Kim, S. V. Kosonocky, and D. R. Knebel. Understanding and minimizing ground bounce during mode transition of power gating structure. IEEE International Symposium on Low Power Electronics and Design, Seoul, Korea, Aug. 2003, 22–25.
5. H. Jiao and V. Kursun. Ground bouncing noise suppression techniques for MTCMOS circuits. IEEE 1st Asia Symposium on Quality Electronic Design, Kuala Lumpur, Malaysia, July 2009, 64–70.
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