Eliminating speed penalties in ECC protected memory designs using “bit bypassing” techniques
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s11767-014-4040-7.pdf
Reference17 articles.
1. Soonyoung Lee, Sang Hoon Jeon, and Sanghyeon Baeg. Memory reliability analysis for multiple block effect of soft errors. IEEE Transactions on Nuclear Science, 60(2013)2, 1384–1389.
2. Onur Mutlu. Memory scaling: a systems architecture perspective. 2013 5th IEEE International Memory Workshop, Monlterey, USA, May 26–29, 2013, 288–292.
3. Jing Guo, Liyi Xiao, Zhigang Mao, and Qiang Zhao. Enhanced memory reliability against multiple cell upsets using decimal matrix code. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22 (2014)1, 127–135.
4. Costas Argyrides, Pedro Reviriego, and Juan Antonio Maestro. Using single error correction codes to protect against isolated defects and soft errors. IEEE Transactions on Reliability, 62(2013)1, 238–243.
5. Xiaoxuan She, N. Li, and D. Waileen Jensen. SEU tolerant memory using error correction code. IEEE Transaction of Nuclear Science, 59(2012)1, 205–210.
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