High-Voltage and Power Transistors
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Publisher
Springer New York
Link
http://link.springer.com/content/pdf/10.1007/978-1-4939-2751-7_7
Reference151 articles.
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2. S. Pendharkar, R. Pan, T. Tamura, B. Todd, and T. Efland, “7 to 30 V state-of-art power device implementation in 0.25 μm LBC7 BiCMOS-DMOS process technology,” IEEE Proc. ISPSD, 419-422, 2004.
3. H. Yang, W.-G. Min, X. Lin, V. Newenhouse, J. Huber, H. Xu, Z. Zhang, B. Peterson, and J. K. Zuo, “Low-leakage SMARTMOS 10 W technology at 0.13 μm node with optimized analog, power, and logic devices for SOC design,” VLSI- TSA, 111-114. 2008.
4. H.L. Chou, P. C. Su, J. C. W. Ng, P. L. Wang, H. T. Lu, C. J. Lee, W. J. Syue, S. Y. Yang, Y. C. Tseng, C. C. Cheng, C. W. Yao, R. S. Liou, Y. C. Jong, J. L. Tsai, J. Cai, H. C. Tuan, C. F. Huang, J. Gong3, “0.18 μm BCD technology platform with best-in-class 6 V to 70 V power MOSFETs,” IEEE Proc. ISPSD, 401-404, 2012.
5. I-Y Park, et al, “BD180 – a new 0.18 μm BCD (Bipolar-CMOS-DMOS) technology from 7 V to 60 V,” IEEE Proc. ISPSD, 64-67, 2008.
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