1. B. Lin, H. Touati, and A.R. Newton, ?Don't care minimization of multi-level sequential logic networks,?Proc. of the IEEE Int. Conf. on Comp.-Aided Design, Santa Clara, CA, pp. 414?417, November 1990.
2. H. Cho, G.D. Hachtel, and F. Somenzi, ?Redundancy identification and removal based on implicit state enumeration,?Proc. of the Int. Conf. on Comp. Design, Cambridge, MA, pp. 77?80, October 1991.
3. O. Coudert, C. Berthet, and J.C. Madre, ?Verification of sequential machines using boolean functional vectors,?Proc. IFIP Int. Workshop on Applied Formal Methods for Correct VLSI Design (L. Claesen, ed.), Leuven, Belgium, pp. 111?128, November 1989.
4. H. Cho, G.D. Hachtel, S.-W Jeong, B. Plessier, E. Schwarz, and F. Somenzi, ?ATPG aspects of FSM verification,?Proc. of the IEEE Int. Conf. on Comp.-Aided Design, Santa Clara, CA, pp. 134?137, November 1990.
5. H. Touati, H. Savjo, B. Lin, R.K. Brayton, and A. Sangiovanni-Vincentelli, ?Implicit enumeration of finite state machines using BDD's,? inProc. of the IEEE Int. Conf. on Comp.-Aided Design, Santa Clara, CA, pp. 130?133, November 1990.