Author:
Salama Cherif,Malecha Gregory,Taha Walid,Grundy Jim,O’Leary John
Publisher
Springer Science and Business Media LLC
Subject
Computer Science Applications,Software
Reference15 articles.
1. Dutertre, B., De Moura, L.: A fast linear-arithmetic solver for DPLL(T). Comput. Aided Verif. 4144, 81–94 (2006)
2. Gillenwater, J., Malecha, G., Salama, C., Zhu, A.Y., Taha, W., Grundy, J., O’Leary, J.: Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee Verilog synthesizability. In: PEPM ’08: Proceedings of the ACM SIGPLAN Symposium on Partial Evaluation and Semantics-Based Program Manipulation, New York, NY, USA, pp. 41–50. ACM, New York (2008)
3. Gomard, C.K., Jones, N.D.: A partial evaluator for the untyped lambda-calculus. J. Funct. Program. 1(1), 21–69 (1991)
4. Hackett, B., Das, M., Wang, D., Yang, Z.: Modular checking for buffer overflows in the large. In: ICSE ’06: Proceedings of the 28th International Conference on Software Engineering, New York, NY, USA, pp. 232–241. ACM, New York (2006)
5. IEEE Standards Board. IEEE standard Verilog hardware description language. Number 1364-2001 in IEEE Standards. IEEE Press, New York (2001)
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Mechanized Semantic Metalanguage for High Level Synthesis;23rd International Symposium on Principles and Practice of Declarative Programming;2021-09-06
2. Compile-Time Extensions to Hybrid ODEs;Electronic Proceedings in Theoretical Computer Science;2017-04-08