High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI
Author:
Kitamura Masayuki,Iijima Masaaki,Hamada Kenji,Numa Masahiro,Notani Hiromi,Tada Akira,Maegawa Shigeto
Publisher
Springer Berlin Heidelberg
Reference6 articles.
1. Shahidi, G., Ajmera, A., Assaderaghi, F., Bolam, R., Bryant, A., Coffey, M., Hovel, H., Lasky, J., Leobandung, E., Lo, H.-S., Maloney, M., Moy, D., Rausch, W., Sadana, D., Schepis, D., Sherony, M., Sleight, J.W., Wagner, L.F., Wu, K., Davari, B., Chen, T.C.: Mainstreaming of the SOI Technology. In: 1999 IEEE International SOI Conference, October (1999) 2. Hirano, Y., Ipposhi, T., Dang, H., Matsumoto, T., Iwamatsu, T., Nii, K., Tsukamoto, Y., Kato, H., Maegawa, S., Arimoto, K., Inoue, Y., Inuishi, M., Ohji, Y.: Impact of Active Body-bias Controlled (ABC) SOI SRAM by using Direct Body Contact Technology for Low-Voltage Application. IEDM, Tech. Dig. (December 2003) 3. Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T., Yoshioka, S., Suzuki, K., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., Sakurai, T.: A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) scheme. IEEE Journal of Solid-State Circuits 31(11), 1770–1779 (1996) 4. Keshavarzi, A., Narendra, S., Borkar, S., Hawkins, C., Roy, K., De, V.: Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC’s. In: Proceedings of International Symposiumon Low Power Electronics and Design, pp. 252–254 (August 1999) 5. Koura, H., Takamiya, M., Hiramoto, T.: Optimum Condition of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs. Jpn. J. Appl. Phys. 39, 2312–2317 (2000)
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