1. International Technology Roadmap for Semi-conductors Home Page, http://public.itrs.net
2. C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White and P. Tobin. “Fermi Level Pinning at the PolySi/Metal Oxide Interface” IEEE Symp. on VLSI Technology Tech. Dig., 2–1, 2003
3. I. De, D. Johri, A. Srivastava, C.M. Osburn, “Impact of gate workfunction on device performance at the 50 nm technology node”, Solid-State-Electronics 44, no. 6, p. 1077–80, 2000
4. J.R. Hauser and W.T. Lynch, “Critical front materials and processes for 50nm and beyond IC devices,” SRC working paper, 1997
5. V. Misra, G.P. Heuss, and H. Zhong, “Use of metal-oxide-semiconductor capacitors to detect interactions of Hf and Zr gate electrodes with SiO2 and ZrO2,” Appl. Phys. Lett. 78, p. 4166, 2001