Exploring SW Performance Using SoC Transaction-Level Modeling

Author:

Moussa Imed,Grellier Thierry,Nguyen Giang

Publisher

Kluwer Academic Publishers

Reference8 articles.

1. Kanishka Lahiri, Anand Raghunathan, Sujit Dey, “Fast Performance Analysis of Bus-Based System-On-Chip Communication Architectures”. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 1999.

2. Frederic Doucet, Rajesh K. Gupta, “Microelectronic System-on-Chip Modeling using Objects and their Relationships”; in IEEE D&T of Computer 2000.

3. A. Clouard, G. Mastrorocco, F. Carbognani, A. Perrin, F, Ghenassia. “Towards Bridging the Precision Gap between SoC Transactional and Cycle Accurate Levels”, DATE 2002.

4. A. Ferrari and A. Sangiovanni-Vincentelli, System Design. “Traditional Concepts and New Paradigms”. Proceedings of the 1999 Int. Conf. On Comp. Des, Oct 1999, Austin.

5. Jon Connell and Bruce Johnson, “Early Hardware/Software Integration Using SystemC2.0”; in Class 552, ESC San Francisco 2002.

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