1. T.A. Riley, M.A. Copeland, and T.A. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis”, Journal of Solid-State Circuits (JSSC), vol 28, no 5, pp 553–559, May 1993.
2. M.H. Perrott, T. Tewksbury, and C. Sodini, “A 27 mW CMOS Fractional-N Synthesizer using Digital Compensation for 2.5 Mb/s GFSK Modulation”, JSSC, vol 32, no 12, pp 2048–2060, Dec 1997.
3. M.H. Perrott, M.D. Trott, C.G. Sodini, “A Modeling Approach for Sigma-Delta Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis”, JSSC, vol 38, no 8, pp 1028–1038, Aug 2002.
4. Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”, Cambridge University Press, 1998.
5. M.H. Perrott, “Fast and Accurate Behavioral Simulation of Fractional-N Synthesizers and other PLL/DLL Circuits”, Design Automation Conference (DAC), 2002, pp 498–503.