Extended BDDs: Trading of canonicity for structure in verification algorithms

Author:

Plessier B.,Hachtel G.,Somenzi F.

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Theoretical Computer Science,Software

Reference14 articles.

1. A. Sangiovanni-Vincentelli, H.-K. Ma., S. Devadas, and R. Wei. Logic verification algorithms and their parallel implementation. InProceedings of the 24th Design Automation Conference, Las Vegas, July 1987, IEEE Press.

2. G.D. Hachtel and R.M. Jacoby Verification algorithms for VLSI synthesis.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 1988.

3. S. Malik, A. Wang, R. Brayton, and A. Sangiovanni-Vincentelli. Logic verification, using binary decision diagrams in a logic synthesis environment. InProceedings of the IEEE International Conference on Computer-Aided Design, Santa Clara, CA, 1988, pp. 6?9.

4. P. Ashar, A. Ghosh, S. Devadas, and A.R. Newton. Combinational and sequential logic verification using general binary decision diagrams. InInternational Workshop on Logic Synthesis. MCNC, Research Triangle Park, NC, May 1991.

5. J. Jain, J. Bitner, D.S. Fussell, and J.A. Abraham. Probabilistic design verification. InProceedings of the International Conference on Computer-Aided Design, Santa Clara, CA, November 1991, pp. 468?471.

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