BADCO: Behavioral Application-Dependent Superscalar Core Models
Author:
Publisher
Springer Science and Business Media LLC
Subject
Information Systems,Theoretical Computer Science,Software
Link
http://link.springer.com/content/pdf/10.1007/s10766-013-0278-1.pdf
Reference27 articles.
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2. Chen, X.E., Aamodt, T.M.: Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. In: Proceedings of the 41st International Symposium on Microarchitecture (2008)
3. Cho, S., Demetriades, S., Evans, S., Jin, L., Lee, H., Lee, K., Moeng, M.: TPTS : a novel framework for very fast manycore processor architecture simulation. In: Proceedings of the 37th International Conference on Parallel Processing (2008)
4. Durbhakula, M., Pai, V.S., Adve, S.: Improving the accuracy vs. speed tradeoff for simulating shared-memory multiprocessors with ILP processors. In: Proceedings of the 5th International Symposium on High-Performance Computer Architecture (1999)
5. Eyerman, S., Eeckhout, L., Karkhanis, T., Smith, J.E.: A mechanistic performance model for superscalar out-of-order processors. ACM Trans. Comput. Syst. 27(2) (2009)
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