Massively Parallel Rule-Based Interpreter Execution on GPUs Using Thread Compaction-Reference-Cited by-同舟云学术

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Massively Parallel Rule-Based Interpreter Execution on GPUs Using Thread Compaction

Published:2020-06-24 Issue:4 Volume:48 Page:675-691
ISSN:0885-7458
Container-title:International Journal of Parallel Programming
language:en
Short-container-title:Int J Parallel Prog

Author:

Köster M.,Groß J.,Krüger A.

Funder

Bundesministerium für Bildung und Forschung

Publisher

Springer Science and Business Media LLC

Subject

Information Systems,Theoretical Computer Science,Software

Link

https://link.springer.com/content/pdf/10.1007/s10766-020-00670-2.pdf

Reference22 articles.

1. AMD: AMD Vega Instruction Set Architecture (2019)

2. Billeter, M., Olsson, O., Assarsson, U.: Efficient stream compaction on wide simd many-core architectures. In: Proceedings of the Conference on High Performance Graphics 2009, HPG ’09, pp. 159–166. Association for Computing Machinery, New York, NY, USA (2009)

3. Campeotto, F., Dal Palù, A., Dovier, A., Fioretto, F., Pontelli, E.: Exploring the use of GPUs in constraint solving. In: Flatt, M., Guo, H.F. (eds.) Practical Aspects of Declarative Languages, pp. 152–167. Springer, Cham (2014)

4. Fung, W.W.L., Aamodt, T.M.: Thread block compaction for efficient SIMT control flow. In: 2011 IEEE 17th International Symposium on High Performance Computer Architecture, pp. 25–36 (2011)

5. Granvilliers, L., Hains, G.: A conservative scheme for parallel interval narrowing. Inf. Process. Lett. 74, 141–146 (2000)

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1. MACSQ: Massively Accelerated DeepQ Learning on GPUs Using On-the-fly State Construction;Parallel and Distributed Computing, Applications and Technologies;2022

2. High-Performance Simulations on GPUs Using Adaptive Time Steps;Algorithms and Architectures for Parallel Processing;2020

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