DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures
Author:
Funder
Deutsche Forschungsgemeinschaft
Publisher
Springer Science and Business Media LLC
Subject
Information Systems,Theoretical Computer Science,Software
Link
http://link.springer.com/content/pdf/10.1007/s10766-020-00688-6.pdf
Reference25 articles.
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2. Bennett, J.K., Carter, J.B., Zwaenepoel, W.: Munin: distributed shared memory based on type-specific memory coherence. In: Proceedings of the Second ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 168–176. PPOPP ’90, Association for Computing Machinery, New York (1990). https://doi.org/10.1145/99163.99182
3. de Dinechin, B.D.: Kalray mppa$$\textregistered$$: massively parallel processor array: revisiting dsp acceleration with the kalray mppa manycore processor. In: 2015 IEEE Hot Chips 27 Symposium, pp. 1–27 (2015). https://doi.org/10.1109/HOTCHIPS.2015.7477332
4. Lenoski, D., Laudon, J., Gharachorloo, K., Weber, W., Gupta, A., Hennessy, J., Horowitz, M., Lam, M.S.: The stanford dash multiprocessor. Computer 25(3), 63–79 (1992)
5. Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M., Miao, C.C., Brown III, J.F., Agarwal, A.: On-chip interconnection architecture of the tile processor. IEEE Micro. 27(5), 15–31 (2007)
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