1. Hareland, S., Maiz, J., Alavi, M., Mistry, K., Walsta, S., Dai, C.: Impact of CMOS Scaling and SOI on Software Error Rates of Logic Processes. VLSI Technology Digest of Technical Papers (2001)
2. Baumann R.C.: Soft errors in advanced semiconductor devices-part I: the three radiation sources. IEEE Trans. Device Mater. Reliab. 1(1), 17–22 (2001)
3. O’Gorman T.J., Ross J.M., Taber A.H., Ziegler J.F., Muhlfeld H.P., Montrose I.C.J., Curtis H.W., Walsh J.L.: Field testing for cosmic ray soft errors in semiconductor memories. IBM J. Res. Dev. 40, 41–49 (1996)
4. Reis, G.A., Chang, J., August, D.I., Cohn, R., Mukherjee, S.S.: Configurable transient fault detection via dynamic binary translation. In: Proceedings of the 2nd Workshop on Architectural Reliability (2006)
5. Segura J., Hawkins C.F.: CMOS Electronics: How It Works, How It Fails. Wiley-IEEE Press, New York (2004)