1. Brown, S. and Rose, J. (1996). Architecture of fpgas and clpds: A tutorial. IEEE Design and Test of Computer, 13(2):42–57.
2. Cheng, W. and Pedram, M. (2001). Low power techniques for address encoding and memory allocation. ASP-DAC Proceedings, pages 242–250.
3. Du, H., M., S.-E., and et al, T. N. (2003). Interactive ray tracing on reconfigurable simd morphosys. ASP-DAC Proceedings.
4. Kamble, M. B. and Ghose, K. (1997). Analytical energy dissipation models for low power caches. Proceedings of the ACM/IEEE International Symposium on Microarchitecture, pages 184–193.
5. Kaul, M., R., V., S., G., and I., O. (1999). An automated temporal partitioning and loop fission approach for fpga based reconfigurable synthesis of dsp applications. Proceedings 36th Design Automation Conference, pages 616–622.