Junction temperature measurement method for IGBTs using turn-on miller plateau duration
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://link.springer.com/content/pdf/10.1007/s43236-021-00275-z.pdf
Reference30 articles.
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4. Choi, C., Lee, J.C.: Bulk and interface trap generation under negative bias temperature instability stress of p-channel metal-oxide-semiconductor field-effect transistors with nitrogen and silicon incorporated HfO2HfO2 gate dielectrics. Appl. Phys. Lett. 98, 063504 (2011)
5. Danković, D., Manić, I., Djorić-Veljković, S., Davidović, V., Golubović, S., Stojadinović, N.: NBT stress-induced degradation and lifetime estimation in p-channel power VDMOSFETs. Microelectron. Reliab. 46(911), 1828–1833 (2006)
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