Investigation of Hetero Buried Oxide and Gate Dielectric PNPN Tunnel Field Effect Transistors
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-020-00716-7.pdf
Reference38 articles.
1. Wu C, Huang Q, Zhao Y, Wang J, Wang Y, Huang R (2016) A novel tunnel FET design with stacked source configuration for average subthreshold swing reduction. IEEE Trans. Electron Devices 63(12):5072–5076
2. Lundstrom M, Ren Z (2002) Essential physics of carrier transport in nanoscale MOSFETs. IEEE Trans Electron Devices 49(1):133–141
3. Saurabh S, Kumar MJ (2016) Fundamentals of tunnel field-effect transistors. CRC Press, Boca Raton
4. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-k gate dielectric. IEEE Trans. Electron Devices 54(7):1725–1733
5. Taur Y, Ning TH (2013) Fundamentals of modern VLSI devices. Cambridge university press, United Kingdom
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