Design and Application of Silicon on Insulator Based SiGe VTFET in IIR Filter by Balanced Truncation (BT) Method of Model Order Reduction
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-02086-8.pdf
Reference39 articles.
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3. Arun Samuel TS, Balamurugan NB, Bhuvaneswari S, Sharmila D, Padmapriya K (2014) Analytical modelling and simulation of single-gate SOI TFET for low-power applications. Int J Electron 101(6):779–788
4. Chander S, Bhowmick B, Baishya S (2015) Heterojunction fully depleted SOI-TFET with oxide/source overlap. Superlattices and Microstructures 86:43–50
5. Yasir M, Samar Ansari M, Kumar Sharma V (2018) Performance evaluation of a FinFET-based dual-output second generation current conveyor. In 2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO), pp. 1–4. IEEE
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