Impact of High-K Gate Stack on Subthreshold Performance of Double-Gate (DG) MOSFETs
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-01891-5.pdf
Reference16 articles.
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2. Toan HLM, Maity SK (2021) Physics based compact modeling of symmetric double gate MOS transistors with high mobility III-V channel material. Superlattice Microst 155:106925. https://doi.org/10.1016/j.spmi.2021.106925
3. Roy R, Chowdhury J, Das JK (2018) Analytical study of double gate MOSFET: a design and performance perspective. Proc 2nd Int Conf Inven Syst control ICISC 2018 625–634. https://doi.org/10.1109/ICISC.2018.8398875
4. Chaudhary R, Mukhiya R, Patel GS, et al (2018) Simulation of MOSFET with different dielectric films. Proc - 2nd Int Conf Intell circuits Syst ICICS 2018 177–183. https://doi.org/10.1109/ICICS.2018.00044
5. Lucky A, Singh BK, Shweta T, Mishra RA (2016) “Short Channel effects (SCEs) characterization of underlapped dual-K spacer in dual-metal gate FinFET device.” IEEE International Conference on Control, Computing, Communication and Materials (ICCCCM) :1–6, https://doi.org/10.1109/ICCCCM.2016.7918265.
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