A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-021-01241-x.pdf
Reference40 articles.
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3. Cho TB, Gray PR (1995) A 10 b, 20M sample/s, 35mWpipeline A/D converter. IEEE J Solid State Circuits 30:166–172
4. Cline D, Gray P (1996) A power-optimized 13-b 5Msamples/s pipelined analog-to-digital converter in 1.2 µm CMOS. IEEE J Solid State Circuits 31(3):294–303
5. Chiaburu L (2003) A method to reduce power consumption in pipelined A/D converters. IEEE Conference, pp I-854- I-848
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