A novel CZP-BC-FLASH ADC using zero phase bubble error robust controller for reliable VLSI circuits

Author:

Kalaiyarasi M.,Saravanan S.,Karunanithi K.,Raja S. P.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Applied Mathematics,Artificial Intelligence,Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Information Systems

Reference24 articles.

1. Zahrai SA, Onabajo M (2018) Review of analog-to-digital conversion characteristics and design considerations for the creation of power-efficient hybrid data converters. J Power Electron 8(2):2–25

2. Jincheol, Yoo, Kyusun Choi, Jahan Ghaznavi (2003) A 0.07µm CMOS flash analog-to-digital converter for high speed and low voltage application. ACM. GLSVLSI’03, April 28–29, 2003, Washington, DC, USA.

3. SumitKhalapure, R.K. Siddharth, Y.B. Nithin Kumar, M.H. Vasantha (2007) Design of 5-bit flash adc using multiple input standard cell gates for large input swing. IEEE Computer Society Annual Symposium on VLSI, p 585–589

4. Renuka Rajaram Jogdand, Pravin Dakhole, Prachi Palsodkar (2017) Low power flash ADC using multiplexer based encoder. In: International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS). https://doi.org/10.1109/ICIIECS.2017.8276157.

5. Talukder Al-Ahsan, Shamim Sarker Md (2013) A three-bit threshold inverter quantization based CMOS flash ADC. ICAEE 2(3):352–356

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